Electronic Design

Power Analysis Plays Key Sign-Off Role

For large designs using nanometer technologies, power and signal-integrity (SI) problems loom as a subtle cause of failed silicon. The impact of IR drop alone can be substantial: In signal and clock nets, a 10% IR drop can result in a 50% variation in timing. At the same time, increased parasitic effects in nanometer designs give rise to noise-related timing problems-and silicon failures for designs that seem to pass conventional sign-off methods. To avoid these problems, companies like Agere Systems now routinely include power and SI analysis as a critical part of their sign-off flows.

"IR drop can have a substantial effect from 130 nm on down, so it's imperative to check its effect on timing during design," says Kevin Stiles, manager of Agere's Signal Integrity and Interconnect Analysis Group. "Reliable power analysis has become essential to provide sign-off confidence, so for the past few years all Agere designs have been going through power analysis before tapeout."

In the past, this type of analysis relied on approximate values for resistance and coupling capacitance. But local process variations found in sub-130-nm copper-based manufacturing processes demand accurate parasitic extraction for uncovering IR drop and noise-induced timing problems. Advanced tools such as Fire & Ice QX, VoltageStorm, and CeltIC NDC work together to analyze the combined effects of parasitic delay, IR drop, and noise coupling to ensure reliable timing closure in nanometer designs.

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