IC designers know the litany backwards and forwards: Area, power, and speed are the primary tradeoffs when it comes to optimizing your designs. You can usually have two out of the three, but a design rarely manages to optimize all of them.
Which of the three is most important to you? Ordinarily, that depends on the IC's end application. However, if you're on the verge of moving to a 90-nm process technology for your next design, the choice has already been made for you: Power is the new sheriff in town. More specifically, you'll likely find yourself losing sleep over power integrity. This isn't to say that the other aspects of design at 90 nm are any less important. (For a broader look at these challenges, see "Think Small: Can You Meet The Design Challenges At 90 nm And Below?" p. 47.)
In Gartner Dataquest's 2004 EDA Market Trends report, chief EDA analyst Gary Smith identifies power-analysis tools as now "as important, if not more important, than timing tools." Moreover, Smith reports that Intel now sees power as "public enemy number 1" at 90 nm and beyond. Hence, Gartner Dataquest's forecast shows significant growth in the power design-tool market through 2008 (Fig. 1). Surging demand is anticipated among designers for tools and methodologies that will help them achieve power integrity in future design cycles.
So what is power integrity? At a high level, it can simply mean ensuring that stable voltage is applied to the IC, hence ensuring reliable operation. But there are many more detailed and intertwining facets to power integrity than that.
One particularly critical aspect of power integrity is IR drop on the power rails that feed the chip. IR drop results from the resistance of on-chip wiring, and at 90 nm, with all feature sizes shrinking, wire resistances are growing.
From the perspective of Sameer Patel, director of Magma Design Automation's design implementation business unit, designers must be aware of two types of voltage-drop issues. "One is dc voltage drop and the other is dynamic or transient drop," says Patel. Too much voltage drop will prevent the logic cells from receiving adequate voltage and functioning as expected. "In other words, timing will be adversely affected."
IR drop is a purely dc attribute, but that doesn't make it simple to deal with. Accurate accounting for IR drop depends on accurate assessment of the currents the circuitry sees, says Graham Bell, director of marketing at Nassda. "There are numerous currents to account for. Among them are supply current, current from on-chip decoupling capacitors, diffusion charge stored in neighboring transistors, crowbar and leakage currents, and load current," Bell says.
With decreasing process geometries and smaller supply rails, IR drop has gained ground as a malevolent influence on design performance. At 1 V, a 200-mV IR drop represents a 20% drain on the chip's supply.
Closely related to IR drop is electromigration, a serious issue that affects power integrity. As supply voltages drop and currents increase, those same smaller, higher-resistance wires are carrying more amperage than they can handle. The result is physical degradation of the power rails, which in turn can create reliability issues in the field. The metal in the wires literally wears away and can cause intermittent or total failures.
Supply voltages on many high-end ICs are now down to 1 V and below, leading to decreasing margins for voltage fluctuation. Those decreasing margins result in an even more pernicious problem: ground bounce. Simultaneous switching noise can cause ground to fluctuate, leading to difficult-to-isolate signal-integrity problems and timing issues.
The lower supply rails in today's ICs mean much less immunity from signal-integrity problems that tie directly into power integrity. "If you have a 1-V supply, a logical zero would be somewhere between, say, 0 V and 0.1 V," says Bell. "A logical one would be between 0.8 V and 1 V. There's this no-man's-land between 0.1 V and 0.8 V."
Stated another way, as a signal transition is occurring, a small transient of, say, 100 mV due to nearby wiring can cause a flip-flop to change state. When voltage rails were at 5 V, designers had a lot more margin for error."You could get away with a 0.5-V transient," says Bell.
There's also the growing concern of leakage power, which, by all estimates, will be a dominating concern at the 65-nm process node. Andrew Yang, chairman and CEO of Apache Design Solutions, says designers can expect a 50× to 100× increase in leakage power at 65 nm compared to 100 nm. "Leakage is already a big problem for companies like Qualcomm and TI at 90 nm," says Yang.
The biggest leakage problem at 90 nm is source-drain leakage, according to Eric Naviasky, VP of engineering services at Cadence Design Systems. "At 90 nm, we can pack two to four times the number of gates per square millimeter of silicon than we used to. But we don't have two to four times the number of power-busing layers. When that's running at 1 V, we could be talking about 10 A or more. That's an electromigration risk," he says.
Smaller geometries and lower supply rails, then, comprise some of the larger obstacles to designers' achieving of power integrity in their ICs. Another aspect is the increasing number of metal layers. "To address this, we can adopt the practice of the power grid, which is helpful," says Naviasky. "But analytically, the power grid is a mess. When you had just a bus, the extractor could break it into a limited number of nodes for analysis. A power grid, though, is made up of tens of millions of elements."
Reaching power integrity adds a verification step that delays the time to tapeout. For some design teams, this step isn't seen as necessary. "In the old days, we used to just overdesign everything and create more robust power rails," says Pete McCrorie, director of product marketing in Cadence's DFM group.
Further, most static timing-analysis tools can't accurately handle the impact of instance-specific operating voltages. "Across the design, you have different instances of circuit elements working with different operating voltages, even though you may think, or assume, that you're supplying a constant voltage," says McCrorie. As a result, few design teams properly validate the impact IR drop has on their circuits' timing.
FITTING INTO FLOWS
There are numerous ways in which power integrity fits into today's design flows (Fig. 2). Generally, designing for power integrity begins with a floorplan for power routing. Also, early on, designers usually make an early attempt to place decoupling capacitors.
"In floorplanning mode, we'll put together dummy blocks with what we believe the current power numbers are," says Naviasky. "Often, even before the blocks themselves are designed or laid out, we can then determine that the power grid needs more metal. Knowing that early in the design cycle can be incredibly valuable."
The floorplanning process can yield other insights as well. "We're seeing an emerging trend toward trying to design the power grid during floorplanning," says Rajiv Maheshwary, senior director of marketing for Synopsys' implementation group. "Doing more voltage-drop-aware floorplanning means that you're analyzing, with some coarse placement of the cells, how much the voltage drop is going to be. It's still an estimate or prediction."
Using voltage-drop-aware placement can also help designers distribute high-current drivers across the power rails. In this fashion, they can avoid local hot spots of IR drop.
Verification of power integrity is used to validate and fine-tune initial calculations regarding power consumption and distribution. Some approaches use hierarchical verification of the power rails integrated with static timing analysis. Others, however, are more attuned to the full chip. "You have to do some static analysis," says Nassda's Bell. "You don't want to do a two- or three-day simulation run only to find that you had a piece of metal in there that you could have screened out using a simpler static technique."
But there's still a need for a dynamic, full-chip verification methodology to achieve power integrity. Otherwise, there's a risk of overlooking possible transient failures. "At 90 nm and 65 nm, people are trying to analyze the dynamic nature of the problem," says Maheshwary. "That means full-chip analysis. You must analyze on-chip and package parasitics. You must simulate dynamic voltage drop across operational modes and across various stages of the flow. And whatever is done on the verification side must be fed back to the implementation tool to either fatten the power grid or, in the case of dynamic drop, place decoupling capacitance."
A SYSTEM-LEVEL APPROACH
In the process of designing for power integrity, IC designers would do well to remember that ICs go into packages, and packages end up soldered to pc boards. "Signal analysis is generally local, but power noise propagates globally," says Jiayuan Fang, president of Sigrity Inc. "It's a system-level issue. To ensure power integrity, one does need to account for ICs, packages, and boards."
Why is it so important to approach power integrity from a system perspective? According to Ching Chao Huang, senior VP at Optimal Corp., package and pc-board ground-bounce issues are much more severe than ground-bounce issues on ICs themselves. "Within the IC itself, we usually assume power and ground inductance of no more than 1 nH. But in the package and pc board together, you might easily see 7 to 10 nH," he says.
IC packages can have hundreds or even thousands of internal power and ground connections, but because the IC's power/ground grid is relatively lossy, noise doesn't propagate well. But once the package is connected to the pc board's relatively low-loss power and ground nets, there's a lot more opportunity for noise to propagate. A system-level approach to simulation enables designers to get a handle on off-chip effects.
Full-system power simulation will move to a point at which power considerations are integrated into the design flow from concept through tapeout. This type of flow must include RTL power estimation and power-grid analysis of ground bounce and IR drop. It also must account for dynamic power including simultaneous switching issues (Fig. 3). "Such a flow requires an analysis infrastructure that can perform a multidimensional dynamic analysis. The analysis needs to be plugged into the flow so it's not an afterthought," says Vess Johnson, CEO of Nascentric.
To achieve low-power design and leakage control, several well-known techniques are being widely used at 90 nm. "The most popular is gated clocks, which dynamically shuts down different portions of the clock network," says Andrew Yang of Apache Design Solutions.
Another technique is multiple supply domains, in which some parts of the design use higher supply voltages, while others use lower voltages. Yet another is multiple voltage thresholds, a technique for trading off performance and power. Segments of the design requiring higher power use a lower threshold voltage, while segments targeted for power savings use higher thresholds.
Leakage control comes from adjusting the threshold voltages, which can optimize or reduce leakage power. Lower thresholds correspond to higher leakage. "You can control thresholds statically, before implementation, by assigning higher thresholds to some portions of the circuit. But static thresholds cannot be changed," says Yang. "More sophisticated approaches use active substrate biasing or power gating, which are dynamically controlled approaches."
Generally speaking, designers must try to understand the impact of IR drop on timing. "In the past, design teams chose to ignore IR drop. Now, they must ask how and where it will cause functional failure," says Cadence's McCrorie. A simple linear derating of delay with IR drop isn't accurate enough. At 130 nm, static analysis can be used where there's sufficient decoupling capacitance. But at 90 nm, static analysis must be supplemented with dynamic analysis, which adds the ability to fine-tune the design for decoupling and leakage.
It's important that designers gain visibility into power-integrity issues as early in the design flow as possible, says Sameer Patel of Magma. "Avoid overdesign of the power grid, especially in the higher metal layers, which are valuable to you in terms of solving congestion problems," he says.
In simulation, designers can capture their pre-layout current demands and check them against initial extractions of post-layout networks. "That's a 'quick-and-dirty' technique that can give you some insights," says Nassda's Bell.
In a paper presented at the recent DesignCon, Optimal's Ching Chao Huang described a technique in which ground bounce is considered separately from power bounce. The best approach, according to Huang, is to strive for equalized power and ground bounce.
"An example is a stripline design with a signal trace midway between the power and ground planes. That signal trace sees the same impedance with respect to the power plane as it does with the ground plane," says Huang. "If there's imbalance, you may be reducing ground bounce but increasing power bounce or vice versa. In the end, it's the maximum that counts. If you have more of one or the other but the absolute combined maximum is larger, you lose your voltage margin."