Electronic Design

Power-Integrity Flow Cuts Out the Guesswork

Thanks to a healthy dose of physical awareness, a power-integrity implementation and optimization tool attacks many facets concurrently.

In many ways, power-integrity closure can be viewed along the same lines as timing closure or signal-integrity (SI) closure. Getting to the point where you're satisfied that your system-on-a-chip (SoC) design meets power requirements can be just as messy as it can with timing or SI. Not only that, but power, timing, and SI are mutually dependent—so much so that repairs to one of the three can cause problems with the others.

With the release of the CoolPower tool, Sequence Design completed a physical power-integrity closure flow that concurrently optimizes power, dynamic voltage drop, timing, and SI for nanometer SoC designs. CoolPower is essentially the next generation of Sequence's Physical Studio tool.

CoolPower comprises a toolkit of power-optimization techniques, some of which are carried forward from Physical Studio. Others, however, are new and quite different from conventional power-integrity flows.

Sequence's overall flow starts with an initial netlist and placement (Fig. 1). In that segment of the flow, nothing changes for the design team. But once CoolPower is fed that netlist and placement, it gains insight into, and awareness of, physical placement. It unifies placement-driven optimization and post-route optimization into a single engine.

As a result, CoolPower knows how and when to implement various power-optimization techniques to address one or more electrical effects at any given time, all the while preserving timing and SI throughout the flow. The tool has demonstrated up to tenfold savings on standby leakage power, 15% to 20% on total power, and 20% on crosstalk delays.

CoolPower uses its insight and awareness to great advantage in two critical areas: power gating and voltage-drop optimization. "We're taking a somewhat radical approach to power gating," says Jerry Frenkil, Sequence's CTO and vice president of advanced development.

A power-gated design uses power switches made from high-VT transistors to sever the connection to power or ground for low-VT standard cells, "turning off" leakage power when the design is in standby mode. Upon receiving the netlist and placement, CoolPower replaces non-power-gated cells with power-gated, or MTCMOS, cells. This cell-swapping is done in keeping with user constraints.

Next, CoolPower inserts and optimizes switch cells (Fig. 2). These cells are placed between the logic cells and ground. The tool automatically determines how many switch cells it needs to insert as well as how it clusters the logic in terms of connection to those switches. The logic's switching patterns and user constraints drive these decisions.

One of these constraints is the maximum voltage allowed on the "virtual ground," the node between the sleep cell and the logic cell. For example, a user can specify that there should be no more than 40 mV on the virtual ground, and the tool will design the virtual-ground network to meet that constraint.

Users control the number of power-gating switches, as well as the maximum distance between them. Based on the design and constraints, the area overhead for the power-gating switches runs from 2% to 6%.

The next step in the process is for CoolPower to size the switches. Sequence's library of switch cells contains multiple sizes, and CoolPower chooses from among them to insert the appropriate size to meet the ground-voltage specification. This is done for each cell, and it can be done before and after routing.

The power-gating approach brings some new design issues that don't arise in non-power-gated designs. If power gating is only applied to a portion of a given design, and the outputs of that portion drive a non-power-gated section, that output node can float when the switch is open. The result is a bad situation for the downstream, non-power-gated logic.

Two capabilities in CoolPower combat this issue. One is electrical rules checking, which searches designs to find these floating nodes. If the tool finds any, it automatically repairs them by inserting an interface buffer that prevents the input to the non-power-gated logic from floating.

VOLTAGE-DROP ISSUES
CoolPower also tackles voltage-drop optimization armed with a healthy dose of physical awareness. The tool features two prime mechanisms for dealing with voltage-drop issues.

The first is to insert and optimize decoupling capacitors to neutralize hot spots. CoolPower first tries to insert capacitors in locations that would otherwise be empty. If there's not enough space, the tool will move cells to create it. But it won't do so if the move will upset timing.

"The effectiveness of decoupling is very dependent on proximity to the high-current-draw cells," says Frenkil. "Sometimes we can do it without modifying the cell placement, and sometimes not. That's where CoolPower's timing awareness comes into play."

User-controllable parameters are in force here, too. Designers can tell CoolPower what their voltage-drop limit is, and it will insert capacitors until that goal is met. Or, designers can instruct the tool to fill an arbitrary amount of space with capacitors, and it will do so with an eye toward achieving optimal results.

CoolPower works hand in hand with CoolTime, Sequence's existing timing-closure tool, to automatically determine distribution of decoupling capacitors. CoolTime performs the dynamic voltage-drop analysis on which CoolPower bases the capacitor distribution. In one case, CoolPower improved a design's dynamic voltage drop by 47 mV simply by optimizing the placement of decoupling capacitors that were already inserted by the designer (Fig. 3).

Available in July, CoolPower starts at $150,000 for a one-year license.

Sequence Design Inc.
www.sequencedesign.com
(408) 961-2300

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