Electronic Design

Power Integrity Tool Saves Weeks In Testing Time

Tomahawk-S, a next-generation power integrity solution, conducts voltage drop, electromigration, and power analysis of current and future system-on-a-chip (SoC) designs. With this tool, SoC designers can run multiple iterations in a single day on massively hierarchical designs, saving weeks when compared with traditional methods. The tool's single-kernel architecture supports power analysis, network extraction, reduction, and simulation. Tomahawk-S processes over 4 million gates in 10 minutes, leading to runtimes of less than one hour for large 25-Mgate designs. Its embedded one-stop hierarchical database eliminates inaccuracies associated with traditional "black-boxing," or the block-by-block abstraction approaches of handling designs with different levels of abstraction. The tool accurately and automatically handles SoC designs containing multiple supplies and frequencies, complex clock-gating schemes, via arrays, C4 bumps and metal slotting, and memories with non-uniform power distribution. Tomahawk-S is compatible with industry-standard formats and easily integrates with existing commercial place-and-route tools. It is licensed on Sun Solaris, HP-UX, and Linux. Annual license pricing, which starts at $150,000, will vary with configuration.

Apache Design Solutions www.apache-da.com; (650) 969-4183

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