The EDA industry is on the verge of another fundamental shift in design modeling techniques. Like many industry changes, however, most trends in electronic design language improvement are cyclical, allowing sensible predictions for future methodologies.
Cracks in the design process are appearing. With the explosion in silicon real estate, existing design methodologies have been stretched to their limits, driving the language-enhancement cycle again. Verification, embedded processors, and overwhelming transistor counts are setting the agenda for the new languages.
Most ICs are designed using either Verilog or VHDL HDLs. A fair assessment of language usage proportions may be derived from the statistical data collected by the Electronic Design Automation Council (EDAC). These numbers reveal a 69% to 31% split between Verilog and VHDL simulation revenue over the last two years.
Even allowing for the lower average selling price of VHDL simulators, Verilog is more widely used. This usage is predominant in the United States and across much of Asia, while European companies prefer VHDL. A further popularity indicator is the number of new EDA tools that work with Verilog before a VHDL version is produced.
Why is this important? Language change tends to be evolutionary in nature. This is inevitable, as users take the path of least resistance. The language choice will be based on minimal investment in new tools, training, and ramp-up time. Knowing which existing language the new methodology will evolve from is critical.
Although some industry commentators would disagree, the need to enhance language usage is clear. New verification-specific utilities driven by their own languages have highlighted test bench deficiencies in existing HDLs. A lack of progress in abstraction improvement has resulted in overly verbose models and elongated design processes, due to unnecessary complexity. Some of the applied short-term process fixes have caused other parts of the methodology to become unwieldy.
Two language choices have emerged as clear favorites—SystemC and Superlog. Each has characteristics that appeal to different users.
SystemC contains architectural and system features. It suits high-level design by designers with knowledge of C++ programming. Superlog contains system, abstract design, and a wealth of verification features. Because it's a superset of Verilog, it's suited to Verilog users who want to expand their existing flow.
The emergence of these two languages gives way to predictions for the future. Verilog users requiring verification and abstraction enhancements, as well as a consideration of embedded processors, can evolve to Superlog. The language permits incorporating new constructs with minimal impact, while providing a number of benefits. It appears that a similar language program doesn't exist on the VHDL side, so what are VHDL engineers going to migrate to?
The SystemC Class Library system resembles a VHDL style of coding. SystemC might represent an evolutionary path from VHDL, albeit disconnected. Furthermore, many system companies using VHDL may relate to SystemC.
Conversely, some VHDL customers have suggested that a move to Verilog would allow them to leverage new tool development, although they would miss the programmable freedom. Superlog represents a solution to this issue.
A quick analysis of the language landscape suggests that evolution, not revolution, will satisfy the needs of new design and verification methodologies. The language that meets these needs, while minimizing design process discontinuity, is the one that will capture the mindset of today's designers.