Electronic Design

Predictive Verification Finds Bugs Earlier

Assertion-based verification has arrived, and tool flows are emerging to take more advantage of assertions early in the design process. An apt example is Atrenta's 1Team:Verify, which brings the benefits of assertion-based verification to RTL designers. The tool leverages assertions early in the game, identifying critical bugs at a stage when they're relatively easy and inexpensive to correct.

1Team:Verify catches many corner-case bugs that traditional simulation can miss. These can include errors involving clock-domain crossings, finite state machines, handshake mechanisms, and bus structures. The tool can check for many of these problems automatically with no user intervention. However, users with more experience can write their own assertions using their favorite assertion language.

Until now, assertion use has required significant expertise and handoff of RTL designs to assertion engineers, who would apply assertions, find bugs, and turn the design back over to the RTL designers. 1Team:Verify can eliminate many of these iterative cycles by allowing the RTL team to carry out many assertion checks itself.

The tool generates and validates a large number of assertions--over 10,000 assertions for a 500,000-gate design, on average--providing a high degree of verification coverage without user intervention. An integrated debug environment helps designers quickly track down the source of errors.

The tool supports the Open Verification Library, which is a stepping stone to the more powerful Property Description Language and System Verilog Assertions. Support for both of those verification languages is available optionally.

A one-year time-based license for 1Team:Verify costs $80,000. It will be available around the beginning of the third quarter. The PSL and SVA options are priced at $40,000 each.

Atrenta Inc.

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