Traditionally, post-layout parasitic extraction has treated device and interconnect models separately. That paradigm falls apart partially at 90-nm geometries and more fully at 65-nm geometries, where complex physical effects are borne of the interaction between devices and the interconnects that tie them together.
Thanks to new resistance and capacitance engines, Mentor's Calibre xRC full-chip parasitic extraction tool gives designers a better look than ever at post-layout silicon electrical effects. In addition to enhanced accuracy, the new resistance engine enables Calibre xRC to offer hierarchical netlisting and optimized back-annotation capabilities between itself and Nassda's HSIMplus simulation platform.
Device geometries are shrinking, and that's taking some of the predictability out of modeling at the device level. For example, accurate modeling of a transistor's behavior now means accounting for many more parameters than simple length, width, and area.
Calibre xRC's new resistance and capacitance engines, combined with Calibre LVS (layout versus schematic), fully comprehend the boundary of the BSIM 4.0 simulation model to accurately measure, extract, and analyze these new parasitics while also producing smaller netlists.
The resistance engine offers enhanced fracturing, including precise width and resistor location for electromigration analysis. The capacitance engine delivers a much tighter correlation to field-solver and silicon data for higher accuracy. Incorporated special models for vias, contacts, and the poly-to-contact area are all susceptible to significant capacitance effects.
The collaboration between Mentor and Nassda gives the companies' mutual customers dramatic improvements in the efficiency of extraction and simulation. Pricing for Calibre xRC starts at $148,000. The tool runs on Solaris, HP, and Linux platforms.