The SP4140 500-Mbit/s read channel chip is claimed to be the fastest, most capable such device available. The CMOS IC lets designers choose between advanced 48/51 and 48/52 codes to increase areal density- the two codes are designed to deliver maximum performance over a range of data conditions with minimum error propagation. And an improved, more efficient Grey code detection system in the servo demodulator of the channel allows designers to shorten the servo burst and ID fields in the embedded servo wedges to increase usable storage by reducing servo overhead. A post processor is provided to deliver the signal processing power needed to reduce bit error rate (BER) at a given signal-to-noise ratio (SNR) or to significantly improve the SNR of the design at a given BER.