Reusable Verification IP Fits Into Overall Automation Planning

Sept. 1, 2006
With its acquisition of Verisity in 2005, Cadence set out on a path toward building an integrated verification methodology that spans the entire design cycle. The latest piece of that puzzle is embodied in a family of verification IP blocks that include

With its acquisition of Verisity in 2005, Cadence set out on a path toward building an integrated verification methodology that spans the entire design cycle. The latest piece of that puzzle is embodied in a family of verification IP blocks that include an executable verification plan.

The Universal Verification Components (UVCs) drive the management of the verification process. They also automatically calibrate, measure, and report on protocol compliance. Cadence plans to provide UVCs for popular protocols including ARM's AMBA, AHB, and AXI; PCI Express; Ethernet; and USB. Each UVC is pre-verified against the protocol specifications.

The verification plans packaged with the UVCs make the compliance requirements explicit and understandable. Also, they fit into Cadence's strategy of reducing the risk in any verification process. The UVCs are reusable across all phases of the design and verification process.

UVCs fit into Cadence's verification process automation methodology, which makes verification more predictable and productive (see the figure). With each UVC comes an executable verification plan that drives all facets of the process. During planning, users can estimate resource requirements (people and computing), assign tasks, and define coverage goals.

The verification plan is executed using automated test generation, simulation, and when necessary, hardware acceleration and/or emulation. Measuring results after each run provides metrics on coverage achieved and the the overall verification process status in terms of the plan. As a result, objective measurement replaces "gut-feel" progress measurement.

An advanced testbench core in each UVC generates scenarios to exercise the design under test (DUT). It includes assertions to check the protocol and interfaces. A mixed-language interface supports all IEEE-standard languages to drive the verification process and connect to the DUT.

UVCs are already in customer use and will be more broadly available in the third quarter. Contact Cadence for pricing.
Cadence Design Systems
www.cadence.com

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