Electronic Design

The Rise Of Transaction-Level Modeling

After many years of expectation, we're finally seeing increased use of generally usable methods of hardware design at an abstraction level higher than RTL. This is more than just behavioral level, as it's been known for a long time. Levels of abstraction are commonly seen as being implemented by translating a language at one level into a language at a lower level, e.g., Verilog RTL to Verilog netlist.

However, there's another way to implement a level of abstraction, and that's via extension. Here, the vocabulary of design is extended to include new objects and operations. The prime example of this is the transaction-level modeling (TLM) set of classes in SystemC. The TLM is a significantly higher level of abstraction than the standard behavioral level, and its advantages are compelling.

In effect, the extension capability of C++ as used by SystemC makes it possible to create arbitrarily high levels of abstraction. Though being able to simulate a system design at such a high level is valuable, the ability to implement the design from such a description automatically becomes a fundamental improvement in design methodology.

The high-level synthesis technology required to achieve this is maturing to the point of general usability. This is largely due to the fact that C++/SystemC allows new levels to be created by extension. And, high-level synthesis tools that can process C++/SystemC can support these new higher levels without significant modification.

Consequently, design at the transaction level will be one of the significant trends in 2006.
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