Electronic Design

Router, Signal-Integrity Tools Complete RTL-To-GDSII Flow

In one fell swoop, Synopsys Inc. of Mountain View, Calif., has completed its RTL-to-GDSII design tool flow with the introduction of two tools built into its Physical Compiler suite. The new tools are Route Compiler, a standard-cell router, and ClockTree Compiler, a clock-tree synthesis tool. Additionally, a crosstalk analysis engine has been added to Physical Compiler.

Route Compiler uses a global routing engine to minimize hot spots caused by short nets. It takes advantage of a constraint-driven algorithm that performs detailed routing for these short nets during global routing (see the figure). The result is a design with reduced via counts and shorter wire lengths, which in turn produces higher manufacturing yields. On average, via counts are 5% lower than those yielded by competing tools. The tool works on multiple processors to provide high capacity for large designs.

Coupled with Route Compiler is a crosstalk analysis engine now built into Physical Compiler. The engine uses 2.5D extraction for calculating coupling capacitance. Signal integrity has been added to the synthesis cost function to address crosstalk problems throughout the design flow. Prevention and repair features include crosstalk-driven placement, net isolation techniques, buffer insertion, driver sizing, and variable width and spacing.

Also built into Physical Compiler, ClockTree Compiler offers 5% to 20% improvements in insertion delay and 5% to 10% improvement in clock skew. ClockTree Optimizer, unlike other tools based on technologies that optimize clock trees one branch at a time, optimizes the complete tree. This results in the best possible clock skew without sacrificing insertion delay. ClockTree Optimizer not only optimizes skew and insertion delay, it also preserves critical-path timing.

This simultaneous optimization is made possible because ClockTree Compiler is built into Physical Compiler and uses an incremental placement technology. Clock buffers are placed at the optimal locations without causing problems for existing placement. All types of gated and nongated designs are supported. The tool also lets users define custom clock trees, including the number of levels, the number of buffers, and routing layers. Power minimization and signal-integrity prevention capabilities are included.

Route Compiler and ClockTree Compiler are offered as add-on options to Physical Compiler. For further information, visit www.synopsys.com.

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