Arriving at RTL code that's really ready for synthesis to gate level is often painful. Between legacy IP, undocumented testbenches, and the unavailability of original design-team members, the code that makes up a design project can be difficult to clean up.
HDL Explorer, Stelar Tools' first offering, simplifies and speeds up the process of getting designs clean at RTL, shortening the design cycle and reducing costs. The later errors are found, the costlier they are to fix. HDL Explorer allows designers and verification engineers to use what Stelar calls "best known methods," or BKMs, to find and repair errors while defining and managing the verification process.
The tool works with users' existing design methods and tools without replacing them. Maximum benefits are derived when using the tool on designs of 2 million gates or more. Users can create new IP, designs, interconnects, and testbenches and stitch blocks together. They also can explore and analyze existing designs and testbenches using various views. Additionally, in larger designs, text files become unwieldy for typical text editors. Using a "smart" editor that combines interactive, intelligent text and smart graphics features, HDL Explorer lets engineers pick the best methods for design creation.
BKMs can help raise the quality of older designs to updated standards. They ensure that blocks pass a required set of checks before the designer moves ahead with the flow. BKMs can be used for many purposes, such as ensuring there is only one clock per module or that naming conventions are followed.
Available now for the Linux and Windows platforms, pricing starts at $7900 for a single-user annual subscription license.
Stelar Tools Inc.