Electronic Design

RTL-To-GDSII Flow Encompasses Embedded Memory Test And Repair

Embedded memories are consuming a growing portion of overall die area. Thus, designers of systems-on-a-chip (SoCs) for embedded systems should consider a design flow that guides users through the process of designing testable and repairable embedded memories.

To that end, Magma Design Automation has paired with Virage Logic to craft a reference design flow that includes insertion of design-for-test (DFT) elements throughout the design, verification, and layout phases of the process. The flow details the techniques used to insert Virage Logic's Self-Test And Repair (STAR) memory system, scan insertion, and the use of automatic test-pattern generation (ATPG) verification inside the Magma Blast Create, Blast Fusion, and Blast Yield environments.

According to Magma's Kam Kittrell, general manager of the company's Design Implementation business unit, more of Magma's users are employing memory built-in self-test (BIST) in a growing portion of their designs. Virage's segment of the flow automates creation, test, and repair of the memories, while Magma's implementation flow automates insertion, placement and routing, and management of memory-repair resources.

The documented reference flow put together by Magma and Virage also addresses the methodology issues of integrating third-party IP. The flow will help users insert the STAR memory system while achieving timing closure within the Magma flow.

An application note describing the reference flow will be available soon.

Magma Design Automation
www.magma-da.com
Virage Logic Corp.
www.viragelogic.com

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