Electronic Design

RTL Synthesis For SoCs Optimized For Large Designs

Offering a fast, high-capacity alternative for register-transfer level (RTL) synthesis of very large ICs, the RTL Compiler is optimized for design larger than 1 million gates with aggressive clock speeds. Built to be compatible with customer-owned tooling (COT) design flows, RTL Compiler sports fast runtimes and brings to the party such features as test insertion and power optimization. New analytic technologies include a global-based optimization engine enabling linear behavior over design and library size; constraint-directed logic, power, and datapath optimization; and highly efficient data representation. The tool's total negative slack optimization increases timing margins to optimize more than a design's critical paths, providing extra timing margin for near-critical nets. The tool is shipping now with a base price of $100,000.

Get2Chip Inc.
www.get2chip.com; (408) 501-9600

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.