In today's verification methodologies, catching and fixing design bugs is often like trying to close the barn door after the horse has bolted. Most bugs are introduced very early in the design cycle, but they aren't caught until the final stages of test and validation. Mentor Graphics' new scalable design-for-verification (DFV) methodology attempts to solve this problem.
The platform is centered on a new release of ModelSim (version 5.8), which supports the complete Verilog 2001 specification. According to Mentor, this is an industry first. ModelSim also now supports the first phase of SystemVerilog 3.1 and offers native support for SystemC 2.0.1 and PSL 1.0 assertions. A built-in assertion engine that hastens integrated debug of PSL assertions aids PSL 1.0 assertions. Verilog performance and capacity are beefed up as well.
On the hardware side, the sixth generation of the VStation emulation system enhances the platform. The new VStationPRO sports capacities of up to 120 Mgates (with a second emulation box).
An important part of the scalable verification methodology is VStation TBX. This software product compiles behavioral code into test benches, eliminating traditional co-simulation bottlenecks in hardware-assisted verification flows. Test benches are compiled directly into the emulator, where they're linked to the verification languages. These transaction-level test benches can reduce HDL regression testing by 20 to 30 times.
The fourth new element of the strategy is the MathWorks' Link for ModelSim software, which enables designers to use intellectual property written for its Matlab and Simulink tools in an HDL verification environment. Designers can verify "golden" models from Matlab or Simulink against the HDL representation of the design.
ModelSim 5.8 pricing starts at $4495. VStation TBX starts at $525,000, which includes a VStationPRO emulator. Emulators alone start at $450,000. Link for ModelSim from the MathWorks costs $2000.
Mentor Graphics Corp.