Electronic Design

Sequential-Logic Equivalence Checker Gains Capacity And Speeds Up Runtimes

Checking functional equivalency between system-level models expressed in SystemC or C/C++ and their corresponding RTL representations is an important step toward making the high-level models useful in implementation. Calypto's SLEC sequential-logic equivalence checker, initially released last year, has been upgraded to even further solidify its position as an essential tool in flows starting from above RTL.

Version 2.0 of SLEC increases capacity by 100 times for system-level designs compared with previous releases. The latest version also dramatically improves runtimes and further simplifies the debugging process with counter-example enhancements.

Successful sequential-logic analysis rests upon the ability to handle large, complex changes in design state and abstraction. In SLEC 2.0, Calypto has extended its sequential-analysis engine with a new algorithm that yields a 100 × gain in handling sequential state changes. Such changes are common when comparing functional system-level designs with cycle-accurate RTL designs. SLEC 2.0 can handle designs where the state and temporal differences are measured in the millions.

Design teams who adopt system-level methodologies can use SLEC to verify and refine their RTL implementations. It enables users to quickly verify RTL refinements without having to run full regression suites. Users can also leverage previously validated designs by making sequential changes such as pipelining and resource sharing.

The SLEC 2.0 product family is available now for use with Verilog, VHDL, SystemC, and C/C++ hardware descriptions. It runs under Linux and starts at $175,000.

Calypto Design Systems
www.calypto.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish