As chip costs escalate, the quest intensifies for DFM signoff models. Although everyone is searching for that one sure way to eliminate the respin nemesis, the challenge grows more daunting as process sizes shrink.
Lithography currently is responsible for up to 40% of the overall yield loss, due to problems ranging from depth-of-focus misalignment effects, to field/aberration and scanner effects. The problem is that the miniaturization of structures on semiconductor chips has advanced faster than the development of lithography equipment. Therefore, the pattern geometries produced on the wafer often are smaller than the light wavelength of the exposure tool, making it almost impossible to produce an accurate image of the reticle on the wafer.
Despite the fact that shorter-wavelength light sources include deep ultraviolet and extreme ultraviolet, a "lithography gap" still lingers between the IC dimension needed and the wavelength of available light sources. At 65 nm and below, model-based proximity correction, RET methods, and lithography simulations simply are not adequate to ensure chip manufacturability. They also cannot guarantee that the performance specifications defined by chip designers are being met. That's because the numerical calculation involved in both OPC/RET methods and in full-chip image verification is accurate only for a limited solution space. Therefore, approximations must be used for the complete solution space.
To bridge the gap between design and printed-wafer results, it is necessary to consider lithography effects upstream in the IC design flow. This DFM approach gives design engineers maximum control of the circuit's electrical characteristics. However, it blurs the traditional division of responsibility between chip designers and process and manufacturing engineers. The need for both fabs and designers to be aware of the issues facing each other actually can cause additional iterations—in effect, escalating chip-development costs instead of lowering them.
The way to truly design efficiently for manufacturing signoff is to locate "hot spots" where distortions would cause yield or performance degradations, and fix those ahead of time. Just as Spice simulates the performance of analog electronic systems and mixed-mode analog and digital systems, microlithography software is available to simulate and optimize the full chip. Fast, accurate simulation on larger areas is key for verifying the pattern to be printed. This verification must include complete wafer topography and comprehensive resist modeling to ensure that the final resist patterns on the wafer match the required design geometry and are manufacturable.
Image verification is very similar to electrical verification in scope. It must refer back to the true physical model or, in the case of resist simulation, chemical model. This analytical model can represent the physical/chemical process at any point in the solution space. However, the inherent limitation of any analytical simulation is that the computing requirement is extremely demanding. This approach, then, is rendered unusable for full-chip image verification, even with today's advanced parallel-processing capabilities.
As a result, today's full-chip simulation tools are based on numerical or table-based approaches. Currently, the parameters populating those tables are created by extraction derived from real physical measurements of test wafers running through a fab. This process is very lengthy and costly, but similar problems have been solved before (for example, on the electrical side). Spice simulation long ago replaced the expensive and time-consuming process of extracting electrical parameters from measured data. There, transistor-level models provide the necessary accuracy to create the parameters for table-based models of a static timing-analysis tool. In a similar way, silicon-accurate analytical lithography models, including resist models, can be used to calculate table-based models for higher-level lithography simulators.
Using such a Spice-like DFM approach can help prevent mask failure at 65 nm and below, ultimately reducing cycle time and costs and speeding time to market. It provides a communication channel between design and manufacturing, and is ideal for helping OPC engineers, memory designers, logic designers, and process designers dramatically reduce costs and improve chip yield.