IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple design rules. Design-rule checking enforced these manufacturing constraints by comparing a characteristic measurement to a threshold value. Layout patterns would either pass or fail these checks, and failures would be fixed to ensure a DRC-clean manufacturing sign-off. It was a fairly reliable process.
Those were the days.
Along came nanometer process technology, in which increasing rates of silicon failure and longer yield ramps initiated a sea change in how designers deal with process constraints. Designers now find they can no longer adequately describe the effects of process limitations and variations using design rules alone. Most urgently, compliance with design rules no longer always guarantees acceptable yields.
Why?
Simple design-rule checks alone can no longer account for the variety and complexity of situations that occur in nanometer processes. For example, unexpected catastrophic layout failures can arise from layout ‘shorts’ and ‘opens’ due to random defects. Further, lithography limitations can cause bridging and pinching.
To ensure high yields when using nanometer process technology, designers require new information and new levels of judgment that go beyond design-rule checking to yield analysis. They need new ways to assess the quality of their designs in light of the more complex process constraints and larger process variations they now face. They need new ways to see the impact these constraints and variations have on the quality of their designs. Finally, they need a new kind of work environment that allows them to understand which of these effects is the most important to address during the process of improving design quality.
Today EDA vendors are hard at work extending the range of tools available to designers to address the challenges of nanometer manufacturing signoff.
First, design-rule checking now incorporates statistical yield modeling, rather than just threshold comparison. Layout database characteristics can now be extracted and represented as statistical distributions. Designers gain insight into the range of results in comparison to both compliance thresholds and recommended rule values. Yield models applied to these results prioritize them by providing the designer with a design quality score. Finally, new visualization tools allow a designer to select the highest priority result and work on it in his or her preferred layout environment.
Next, designers can now apply two advanced analytical techniques—critical-area analysis and litho-friendly design checking—during signoff to improve design quality and design robustness.
Critical-area analysis enables the designer to understand a layout’s sensitivity to a range of defect sizes. It also provides an estimate of cumulative particle yield impact by combining layout sensitivity with actual particle size distributions expected during manufacture.
Litho-friendly design checking transforms the complexities of the lithography process into simple DRC-like results that guide designers to weak points in the layout. These weak points represent portions of the layout at risk of bridging or pinching due to variations in the lithography process.
Finally, designers will soon be able to combine the results of all four of these techniques—design-rule checking, statistical yield modeling, critical area analysis and litho-friendly design checking—to arrive at a comprehensive picture of design quality.
Integrated circuit designers are a lucky bunch. While the risks associated with manufacturing sign-off have increased markedly with the onset of nanometer process technology, design rule checking has evolved to yield analysis, enabling designers to meet these new challenges and achieve high quality, production-worthy designs.