Electronic Design

Simulation Demonstrates PCIe Core IP's Capabilities

Intellectual property (IP) provider CAST Inc. has created a free, downloadable simulation model of its PCI Express (PCIe) IP core. The PCIe Core Backend Model (CBM) Demo of the CAST CPXP-EP PCI Express endpoint controller enables designers to simulate a system with the core at the transaction-layer level. Prepared test cases and scripts and an included design example illustrate the features and functions of a PCIe endpoint controller. Multiple parameters and the ability to program a custom application facilitate the experimentation with and learning of this popular interface technology. The PCIe CBM Demo is free to qualified designers after online registration at www.pciexpresscores.com.

The CPXP-EP implements a PCI Express endpoint controller that complies with PCI Express Base specification 1.0a, including the Transaction, Data Link, and Physical protocol layers. The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications, x1 (single lane) and x4 (four lane), and offers bi-directional data rates from 250 Mbytes/s (x1) to 1 Gbyte/s (x4). The core supports most advanced PCI Express capabilities, including message-signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy check, and power-management features. Multilane versions of the core support lane reversal and polarity inversion.

For more information, check out www.cast-inc.com.

TAGS: Intel
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