Electronic Design

Simulator Adds Assertion IP And Native SystemVerilog Support

The latest release of the VCS verification environment sports new capabilities that help users find more bugs more quickly, with up to a fivefold increase in verification speed (see the figure). Key new features include a new assertion IP library and native testbench support for SystemVerilog.

The VCS assertion IP library contains a set of checkers that can be used with VCS or with Synopsys' Magellan formal-analysis tool. The IP library lets users perform functional checks during simulation, identify and report protocol violations, and capture assertion-coverage data. Designers also can use the library with Magellan to prove complex design properties.

Included with the library is IP for a range of interface and protocol standards, including PCI and PCI-X 2.0, AMBA 2 AHB and APB, 802.11a-g, SMIA, DDR2, OCP 2.0, and LPC. Also new to VCS 2005.06 is native support for the IEEE P1800 SystemVerilog testbench. VCS users can create verification environments using SystemVerilog's object-oriented, constrained-random stimulus and functional coverage capabilities.

VCS 2005.06 is expected to ship in the third quarter. Pricing starts at $25,480 for a one-year subscription license.


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