Electronic Design

SoC Co-Verification Suite Takes The Crown For Speed

Hardware/software co-design is one of the frontiers of leading-edge system-on-a-chip (SoC) design. Adveda's flagship Miss Univers co-verification product targets this aspect of the design process by performing combined hardware/software cycle-accurate simulations 100 times faster than competing products.

Hardware and software co-verification methods involve connecting an instruction-set simulator (ISS) and debugger with a hardware simulator via a third tool, yielding three simulation kernels and slow execution times. Miss Univers is a unified hardware/software co-verification tool with one simulation kernel that directly steers RTL models and instruction-set simulation models. It eliminates the integration overhead that has manifested itself in awkward data exchanges and speed penalties.

The Miss Univers hardware simulator is a cycle-based RTL simulator that can accelerate an RTL simulation up to 100 times faster than traditional event-based simulators. It can handle the fully synthesizable RTL syntax, including multiple asynchronous clocks, asynchronous resets, and tristate signals. The initial production release will support VHDL.

The ISSs are built with proprietary technology that allows cycle-accurate instruction-set simulations over 1 Mcycle/s. An integrated development environment (IDE) includes editors for both the embedded software and RTL source code. The IDE also has robust debugging capabilities.

Because the hardware and software simulation is truly unified in one simulation kernel, the debug functionality of both worlds can be mixed. For instance, designers can view registers from an ISS in the waveform view mixed with hardware signals. Or, they can select hardware registers and see them within the register view of the processor.

Full production begins in March. Pricing for time-based licenses starts at $25,000. Adveda also offers the RTL simulator and ISS/IDE products separately, with RTL simulator pricing starting at $10,000.


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