Electronic Design

SoC Design Tool Performs Routing, Physical Optimization

NanoRoute-SI is a system-on-a-chip (SoC) design tool that concurrently performs timing-driven, noise-prevention routing, RC extraction, timing and noise analysis, buffer insertion, gate sizing, and logic restructuring as well as incremental placement within a single product. It incorporates the same graph-based routing engine as the firm's NanoRoute SoC router, combining the flexibilities equal to those of gridless routers and speed and capacity superior to grid-based routers.

A placed-design-to-GDSII capability complements existing design planning and physical-synthesis tools, eliminating costly design iterations. There's also support for physical design data, design constraints, and timing libraries in standard formats such as LEF/DEF, SDC, .lib, SDF, and GDSII, allowing easy adoption and integration into popular design flows with minimal adoption costs and learning curve.

NanoRoute-SI is available immediately. Pricing for a single-CPU configuration of NanoRoute-SI starts at $180,000 for a one-year, time-based subscription license.

Plato Design Systems Inc.
(408) 436-8612; www.platodesign.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish