EE Product News

Software Allows For Mixed-Language Designs

Said to eliminate the distinction between VHDL and Verilog simulators, ModelSim Language Neutral Licensing (LNL) offers ASIC and FPGA designers more freedom to design in a language mix that is appropriate for their particular design. With the program, designers will have the flexibility to simulate either VHDL or Verilog with a single license and a single simulator. They can seamlessly move between VHDL, Verilog, or mixed HDL.

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