Last fall, Carbon Design's DesignPlayer engines let designers validate system software before silicon was available. The company has expanded its reach into hardware by enhancing the DesignPlayer engines. Now, designers can plug the engines seamlessly into hardware regression environments. A variety of testbenches can drive the cycle-accurate and register-accurate runtime models, which are compiled directly from RTL.
DesignPlayer improves regression performance for verification environments, which can include standard testbenches like Vera, e, transaction-level, behavioral Verilog, C, C++, and SystemC. It can improve regression performance up to 10 times compared with current simulators. It also provides interoperability with popular simulators, including Cadence's Incisive and Synopsys' VCS.
Engineers who apply behavioral Verilog, Vera, or Verisity e-based testbenches in a simulation regression environment improve their performance by simply plugging in an optimized DesignPlayer to replace their RTL model. Verification teams using DesignPlayer with C, C++, or transaction-level testbenches (without a simulator) can gain a 10× to 20× regression performance boost compared with RTL simulation while maintaining cycle and register accuracy.
In addition, DesignPlayer now has an automatically generated SystemC interface. As a result, it can be instantiated in a SystemC environment. This benefits designers who use SystemC early in the development cycle for faster simulation.
DesignPlayer products are shipping now. Pricing is based on an annual subscription model. DesignPlayer engines used for development cost under $10,000 per seat at high volumes, while IP distribution versions approach $1000 per seat.
Carbon Design Systems