EE Product News

Software Spots Testability Problems

TurboCheck provides fast feedback on potential design and testability problems during the design phase of a circuit, allowing changes to be made early in the design process. Available in two versions (TurboCheck-RTL and TurboCheck-Gate) to support different levels of checking throughout the design cycle, the program analyzes the testability of sequential circuits and assists the designer in selecting test solutions that are most likely to improve the circuit’s final fault coverage. It operates on non-scan, partial-scan or full-scan circuits. TurboCheck RTL identifies testability problems at the earliest stage of the design cycle, immediately after RTL coding. TurboCheck-Gate is used after the design is synthesized into gates.

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