Version 8.0 of QuickWorks development software adds full support for the firm’s QL5032, a 32-bit/33-MHz master/target device, its complete QuickRAM ESP family of devices, and its three pASIC FPGA families. In addition, the new version provides module generation for logic synthesis and much faster placement times, it’s claimed.A host of general-purpose improvements have been made to the tool. These include cross-probing of schematic nodes during simulation, availability of an optional VHDL simulator from VeriBest, a 32-bit upgrade for the schematic editor, turbo writer and waveform editor, and improved setup times for QuickRAM and pASIC 3 devices. Also, placer algorithm enhancements have resulted in claimed run-time reductions of up to 74% for all device families.Included in the software is VHDL, Verilog, schematic and mixed-mode design entry. Fast, efficient logic synthesis is provided through integration of Synplicity’s Synplify Lite tool, which has been tuned for the ESP architecture.