Software Verifies Complete Systems

Complete systems, including hardware, software and test benches, can be verified with VERA-SV. The software provides an automated virtual prototype where both hardware and software verification can proceed concurrently long before the first physical prototype is built. It addresses the complete verification needs for systems-on-chips and can automatically generate functional tests that mimic the target environment for the chips, thereby creating a virtual prototype complete with all the software, including device drivers and application code. During simulation, the software can monitor coverage points in the design and/or in the generator and use the results to generate new tests to cover untested areas. This feedback loop, coupled with directed, random and constrained random test generation, facilitates quick convergence on high-quality tests, it's claimed. The system supports both Verilog and VHDL.