According to Intel, the number of silicon bugs that need to be eliminated before tapeout is increasing over 200% per generation, a rate even faster than a Moore's Law increase. Evidently, each generation of hardware is not just bigger, but the interactions among those increased numbers of components are increasing even faster, outpacing the development processes that engineers rely on to prevent bugs from finding their way into code and throwing an ever-increasing burden on the verification team. In the absence of dramatically improved productivity in the verification methods, it looks like verification is going to require growing numbers of engineers, time and money.
While there have been some recent improvements in RTL verification technology, today's reality is that hardware-based approaches are needed to verify RTL against real-world system conditions, and do so in a reasonable range of cost and time. Modeling the entire system in higher-level software languages like C offers faster simulation, but still does not take away the need for more exhaustive and hardware-specific testing at RTL. There have been many attempts to compile software languages directly into hardware, but the effectiveness of this approach in the general case is still not high, and there are many limitations. And while lots of R&D is going into this area, a solution is not expected any time soon. By comparison, the problem of creating parallel hardware from sequential software has eluded the computer science community for decades.
At the RTL, assertion technology is improving productivity by making it easier to identify bugs with complex time-dependent origins, but fundamentally we are still dealing with four approaches to RTL verification: simulation, simulation acceleration, emulation and hardware prototyping. These products can be mapped into dimensions of speed, cost, and debug visibility (Fig. 1). Simulation is slow, but it is inexpensive and bug visibility is excellent, especially with assertion use. Simulation acceleration is much faster, but rapidly escalates into cost prohibitive territory while maintaining good visibility.
FPGA prototypes are moderate cost and 10X to 1000X faster than alternatives. This speed permits prototypes to run real software, interacting with real hardware and live stimulus streams. These performance levels permit the exploration of a much wider range of system behavior more thoroughly and in less time than with any other method. Unfortunately, debug visibility in FPGA prototypes is lower than other methods, limiting its adoption.
To really make progress on the verification challenge, the industry needs a technology that combines the speed and cost advantages of FPGA prototypes with the debug visibility of a simulator and the power of assertion-based verification (Fig. 2). Synplicity's TotalRecall technology development aims to solve this critical problem. With that technology comes a new level of productivity and coverage that will help to reverse the tide of pouring more money and human resources into RTL verification; given the 70% of design team resources that currently go into verification, that solution will truly be revolutionary.