Stacked-Die EDA Initiative Harnesses 3D Integration

Mountain View, Calif., USA: Synopsys unveiled an EDA-based solution for stacked multiple-die silicon systems that exploits 3D IC integration. Available now in beta, it includes enhanced versions of the company’s IC implementation and circuit simulation products. Production is slated for the second quarter of this year.

NewsLine-April-2012- News-AVX-ANewsLine-April-2012- News-AVX-AThe 3D integration of die using through silicon vias (TSVs) promises decreased footprints and power consumption. However, multi-die stacks incorporate different materials bonded together with different coefficients of thermal expansion (CTEs). Thus, any temperature change causes material stress, affecting transistor performance. TSVs, microbumps, and other solder bumps also produce a permanent stress in the zone immediately around them. Therefore, chip layouts must be planned carefully.

Synopsys’ 3D IC EDA solution incorporates a number of features:

  • DFTMAX test automation, which performs design for test for stacked die and TSVs
  • DesignWare STAR Memory System IP for integrated memory test, diagnostics, and repair
  • IC Compiler, which provides place-and-route support including TSV, microbumps, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation, and interconnect checks
  • StarRC Ultra parasitic extraction, including support for TSV, microbump, interposer RDL, and signal routing metal
  • HSPICE ad CustomSim circuit simulation for multi-die interconnect analysis
  • PrimeRail for IR-drop and EM analysis
  • IC Validator for implementing DRC for stacked die
  • Galaxy Custom Designer for making specialised edits to silicon interposer RDL, signal routing, and power mesh
  • Sentaurus Interconnect TCAD tool for analysing thermomechanical stress caused by TSVs and microbumps in multi-die stacks
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