Electronic Design

Standard-Cell Optimization Flow Pumps Yield, Tightens Area

Manual and automated IC-layout tools are integrated in the PEYE Yield Finder analysis software. The combined yield-driven, standard-cell, design optimization flow facilitates the application of design-for-manufacturing (DFM) techniques with detailed process manufacturing data.

Two factors determine the number of good die you can get from a wafer: yield and number of die (defined by design area) per wafer. Though yield plays the major role once a design is finished, die area and yield can be balanced in the design phase. DFM factors such as via duplication, wire optimizations, and preferred spacing may sometimes increase area. But with the PEYE Yield Finder analysis tool, users can obtain optimum yield gain versus area growth.

Standard cells—the basic building blocks of modern IC design—are used repeatedly and can limit yield. Standard-cell libraries are freely available, but are typically not optimized for a specific product and process line. Recommended DFM design rules are rarely used because their broad application can increase die size by an unacceptable amount.

The PEYE Yield Finder flow, which integrates manual and automated design tools from Cadence and Nangate, makes it possible to integrate critical area analysis and process-specific yield models into the standard-cell layout process. The result is not only identification of probable faults, but also reduction of these faults. This takes place within the design process and in an area-efficient manner. Rather than using recommended DFM rules blindly, the flow allows use of optimal spacing to maximize yield and minimize area. The resulting yield savings can then be calculated.

For more information, visit http://www.icyield.com

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