Electronic Design

Standard Cell-Optimization Tools, Originally For IDMs, Now Seek To Penetrate Fabless Market

At its introduction almost three years ago, Zenasis Technologies' ZenTime was marketed as a standard cell-optimization tool largely for integrated device manufacturers (IDMs). But Zenasis has broadened its horizons and business model by breaking ZenTime out into an expanded product line that specifically addresses optimizations for leakage power, timing, and area—all concerns for fabless shops.

Zenasis has now adopted a platform-and-plug-in-module approach as opposed to a one-size-fits-all approach. The original ZenTime product, now known as ZenTime-XT, targets transistor-level cell optimization. It creates design-specific cells on-the-fly to improve critical-path timing.

For gate-level timing optimization, ZenTime-GT dips into the netlist during optimization to perform gate sizing using existing standard cells. It performs buffer-tree construction and restructuring, optimizes placement, and then produces GDSII for the optimized cell.

If area optimization is critical for you, ZenTime-AT is a module for the two platform tools that recovers area impacted by timing optimization. It will replace larger cells with smaller ones if doing so doesn't degrade performance in critical paths.

ZenTime-PT is another module that optimizes for leakage power. It operates in multi-and single-VT design flows, allowing users to plot tradeoff curves comparing leakage power to timing and to choose the tradeoff that best fits their needs.

ZenTime-GT, -PT, and -AT are available now. Pricing is variable, but a ballpark starting price for the two platform products, ZenTime-XT and -GT, is around $250,000. The ZenTime-PT and -AT modules cost around $150,000 each.

Zenasis Technology Inc.

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