Electronic Design

Standards Boost SoC Test

Demand for intellectual-property (IP) reuse is rising as the IP market grows. According to Dataquest, 80% of systems-on-a-chip (SoCs) will integrate reusable IP cores by 2005. Testing cores with sometimes questionable provenance is a challenge.

Kicking off an initiative based on an open standard, Synopsys has delivered a test automation methodology to augment its Galaxy design platform. The SoC test automation, available within the SoCBIST add-on to Synopsys' DFT Compiler tool, is based on the open IEEE P1450.6 Core Test Language (CTL) standard. In addition, the ARM-Synopsys Reference Methodology now includes automation of SoC test for use with ARM IP core-based design flows.

The DFT Compiler SoCBIST automates the creation and integration of IP cores optimized for test reuse. First, DFT Compiler automatically synthesizes test-reuse IP cores and creates CTL test models for them. Synopsys' TetraMAX automatic test-pattern generation tool then creates reusable test patterns for those cores. Finally, the SoCBIST tool reads the CTL models of these cores and automatically integrates the cores into the overall SoC, reusing pre-supplied core test patterns referenced from the SoC-level pattern set.

The DFT Compiler SoCBIST add-on starts at $175,000 for a one-year technology subscription license. The initial release supports Sun Solaris and HP-UX platforms.

Synopsys Inc.
www.synopsys.com

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