The cornerstone of system-on-a-chip (SoC) productivity in SoC design is reuse. For reuse to be truly productive, it must be at a high level using large subsystem-level building blocks. But the process of pulling together the IP required to assemble an SoC can be a tedious one with a great deal of manual labor. Not only must the design team come up with the implementation IP, but it also must build a suite of verification IP for simulation.
Through a flurry of partnerships with leading IP vendors, Synopsys Inc. of Mountain View, Calif., has taken IP reuse to another level. The industry's number three IP vendor has added microprocessor cores from Infineon, MIPS Technologies, and NEC to its DesignWare IP library. These cores will integrate seamlessly into DesignWare's AMBA-based on-chip bus IP solution to provide complete plug-and-play microprocessor subsystems.
"We're helping our customers move up a level in abstraction and productivity," says Phil Dworkin, director of marketing and business development for DesignWare. "It's important to us to maintain our existing business model, so we're partnering with star-IP providers instead of producing our own star IP."
Synopsys is developing a complete AMBA-based on-chip bus solution that, when combined with the Star IP cores in DesignWare, lets designers create complete AMBA-based microprocessor subsystems (see the figure). Along with the existing DesignWare MacroCells, Synopsys is adding AMBA on-chip bus logic and other standard microprocessor peripherals to DesignWare. DesignWare customers will be able to configure, assemble, synthesize, and verify AMBA-based subsystems automatically by using new tools built on the proven coreBuilder and coreConsultant technology.
The initial microprocessor cores that will be available through DesignWare include Infineon's C166S, the MIPS32 4KE processor core family, and NEC's Nx85E-STAR (V850). Design Views consisting of configurable simulation and timing models for these cores will be available in DesignWare to existing customers at no additional charge. DesignWare customers who license these cores will also get full Implementation Views of the respective cores in DesignWare, including the synthesizable register transfer level (RTL).
Each microprocessor core will have an AMBA AHB interface for compatibility with DesignWare's on-chip bus solution and other AMBA-based DesignWare IP. These microprocessors will conform to the strict design reuse coding guidelines and methodology defined by the Reuse Methodology Manual (RMM) co-authored by Synopsys.
Star IP cores in DesignWare are packaged into coreKits with coreBuilder. They include the configurable core and a complete verification environment consisting of simulation models, test benches, and test suites. These coreKits are delivered in DesignWare with coreConsultant, a tool that automatically configures the core and verification environment. Additionally, it synthesizes the core using Design Compiler, Physical Compiler, or FPGA Compiler II.
The first Star IP microprocessor cores will be available to DesignWare customers starting in the fourth quarter of 2001. The DesignWare AMBA-based on-chip bus solution will be available in the first calendar quarter of 2002. There is no additional charge to DesignWare customers for the Star IP microprocessor core design views and DesignWare AMBA-based on-chip bus solution. Star IP implementation views are licensed directly from the respective Star IP owners, except the NEC V850, which is licensed from Synopsys. A DesignWare one-year technology subscription license (TSL) costs $25,740.
For more information, visit www.synopsys.com/designware/.