The Japanese Semiconductor Technology Academic Research Center (STARC) has adopted Altos Design Automation’s cell characterization technology as the basis for its statistical static-timing analysis (SSTA) design flow. The STARC adoption of the Altos technology comes on the heels of the Silicon Integration Initiative’s (Si2’s) adoption of the same technology as the basis for its Open Modeling Coalition (OMC) SSTA flow. Si2 has proposed the latter for broad EDA industry adoption.
STARC is developing a manufacturing-aware design methodology named STARCAD-CEL that addresses the challenges of very advanced process technologies including 65 nm, 45 nm and 32 nm. The STARCAD-CEL design methodology will be shared amongst the top Japanese semiconductor companies that comprise STARC’s membership as a standard digital design platform. Within this flow, STARC will use Altos Design’s Liberate to create libraries for design implementation including ECSM and CCS timing, noise and power views. Meanwhile, Altos Design’s Variety will be used to build libraries for statistical timing analysis (SSTA) signoff.
Liberate is a fast library creation tool that generates electrical models in Liberty format. The tool supports all the latest models for timing, noise, and power, such as Composite Current Source (CCS) and Effective Current Source Models (ECSM). Liberate also supports low-power design styles that include power-gating cells, state-retention registers, and level shifters.
Variety characterizes models for multiple SSTA tools. These models include nominal timing information plus additional data representing the impact of any number of parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety can characterize for both systematic and random variation including linear and non-linear effects.For more information, visit http://www.altos-da.com.