Electronic Design

STARC Settles On A 65-nm Lithography Simulator/Analyzer

Following a three-month evaluation, the Semiconductor Technology Academic Research Center (STARC) has tabbed Blaze DFM’s Halo for lithography simulation and analysis. The tool will be integrated into STARC’s STARCAD-CEL (Certified Engineering Linkage) reference design flow.

With its STARCAD-CEL methodology, STARC, which is Japan’s foremost semiconductor technology research organization supported by Japanese IDMs, hopes to establish a process-friendly and low-power reference flow that strives to eliminate manufacturing uncertainty in sub-65-nm system LSI designs.

STARC evaluated Blaze DFM’s Halo using three 65-nm designs, as well as with multiple rule sets and process windows, to identify lithographic errors, or “hotspots,” on all metal and via layers. They also measured the scalability of Halo using different configurations of one, two, four, eight, 16, and 27 processors.

The silicon image representation produced by Halo consists of a collection of manufacturing-centric variants of the physical integrated-circuit design, including the original layout, a version of the layout as printed in silicon, and a series of error vectors that identify potential lithographic hotspots.

Halo is plug-compatible with existing standard EDA design flows. By utilizing an accurate physical representation of the design as printed in silicon, this approach facilitates improvements in yield, predictability, and performance using existing design tools.

Blaze DFM Inc.


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