As semiconductor manufacturing heads toward 45 nm as the next mainstream node, the 32-nm node is next on the horizon. But the wavelength of the light sources used to print circuit patterns on silicon is stuck at 193 nm for the foreseeable future. There’s not much wiggle room on the optical side of the equation, either. Thus, the theoretical limits of today’s lithography technology loom as a potential Moore’s Law killer.
But Tela Innovations, a San Jose-based startup, sees an opening for innovation on the design side that might just give Moore’s Law a little more time. One circuit design technique that could come into play at sub-45-nm design rules is double patterning, which entails separating the design into two masks and printing on silicon twice. This takes pressure off in terms of resolution, but it shifts the emphasis onto alignment.
In a sub-45-nm lithography world where alignment matters as much, if not more than resolution, the physical limitations of the lithography technology can really skewer the design team. Two-dimensional patterns with jogs and bends in the interconnects become harder to print than ever, because corners and rounded shapes simply do not print cleanly.
Tela’s answer to this problem is a cell-authoring system that converts user-supplied cells into Tela cells that adhere to pre-defined topologies. These topologies employ strict application of one-dimensional, on-grid layouts with fixed pitches and widths. Among the benefits Tela claims for its approach are area reductions of 10% to 15% as well as leakage-power reductions up to two-and-a-half times.
Tela’s cells, which are known as “T cells”, will eventually encompass about 60 different topologies. Because they’re so regularly patterned, the cells reduce the interactions between shapes that lead to variation in manufacturing. This is in contrast to typical design-for-manufacturing (DFM) approaches that try to tackle variability by moving two-dimensional structures around in relationship to each other.
Perhaps an even more important point, Tela’s topologies provide a direct path to double-patterned layouts in the future. The topologies, which are applicable to logic circuits, embedded memories, analog circuitry and I/Os, are easily split for double patterning.
The business plan for Tela is essentially an IP model in which the technology is licensed to customers. Upon engaging with customers, Tela will configure a base library of T cells for them in a service mode. The customer would then have access to the cell-authoring system for subsequent modifications or additions to that library.
Contact Tela directly for pricing and delivery information.