Rising design complexity causes innumerable headaches in achieving functional design closure. Startup firm Blue Pearl Software plans to address design closure at RTL using a combination of design-rule checks. Its ultimate goal is to cut down on design iterations by resolving critical timing-path and design-for-test (DFT) issues.
Functional design closure processes require early identification of RTL errors. This is typically accomplished by synthesizing RTL down to the logic level and applying structural rules. Blue Pearl's methodology will operate at RTL using symbolic simulation and state-space exploration. Its tools will use design-rule checking without first synthesizing to gates.
The tools will check for complex issues like clock-domain-crossing problems, initialization, and finite-state-machine behavior verification. They'll identify false paths and automatically generate timing constraints.
Early DFT closure is a byproduct, as the tools will find testability problems prior to synthesis. Checks based on RTL test procedures will locate DFT clocking and reset issues that would upset downstream scan-chain operations if not found at RTL.
The software will operate on full-chip designs, automatically checking that each branch in the RTL code is possible. It will check for set-reset conflicts, bus conflicts, bus floats, and many other common bugs.
Blue Pearl's first products will roll out in the third quarter of 2004.Blue Pearl Software Inc.