For some SoC hardware designers, the use of algorithmic expression to define a system in behavioral terms may enable faster simulation. But it also can obscure significant details, such as how much pipelining is contained within the system.
Startup Bluespec has stealth-launched a tool based on MIT technology that takes a very different approach to high-level design. Rather than starting with algorithms written in C/C++, Bluespec proposes that design functionality be expressed in SystemVerilog with the addition of assertions. But Bluespec's use of assertions is quite different from those already present in SystemVerilog.
To Bluespec, assertions are represented in the technology licensed from MIT as "Term Rewriting Systems" (TRSs). The key difference between Bluespec's assertions and those in SystemVerilog is that Bluespec's are a declarative means of expressing intended system behavior. In SystemVerilog, assertions are used after the fact to verify intended functionality.
TRS technology reveals details that can be obscured by high-level design in C. In the TRS technology, designers can specify many functions as rules that occur concurrently in time. The Bluespec tool automates the synthesis of a controller, or scheduler, that dynamically examines circuit conditions on each cycle and determines which rules can or cannot execute on the next cycle. As a result, the use of TRS technology eliminates the possibility of race conditions.
Designers using Bluespec technology would begin by coding in BlueSpec SystemVerilog, which contains the TRS assertions. Bluespec's compiler provides the functionality expressed in that code as Verilog 95 and/or a cycle-accurate C model for simulation. The Verilog 95 output is then used as input for Synopsys' Design Compiler for synthesis to a gate-level netlist. Because the RTL produced from Bluespec's compiler is governed by the compiler-generated controller, that RTL is described as "correct by compiler."
Bluespec plans to formally release its toolset in the second quarter. Pricing hasn't been set as of this writing.