Electronic Design

Startup Looks To Close The Gap Between Manufacturing And Design

With 90-nm semiconductor processes ramping up, foundries and integrated device manufacturers find themselves in a quandary. They've been relying on very aggressive resolution-enhancement technology (RET) to get by on 193-nm lithography. The resulting tool runtimes and mask data volumes are becoming impossible to handle.

Aprio Technologies, a Santa Clara-based startup, may have an answer. It will soon release tools based on technologies that fundamentally speed up and simplify the way RET is applied to mask data.

"The problem lies in the fact that no tools manipulate process, geometry, and circuitry all at the same time," says Clive Wu, Aprio's CEO and CTO. "Only geometry is used to communicate between the design back end and the manufacturing front end."

Aprio's approach to RET hinges on at least two core technologies. First, a fundamental data structure allows the building of applications that address process, geometry, and circuitry. This data structure, known as the Trinity data model, lets design intent pass downstream while process effects pass upstream.

The second core technology is a reconfigurable RET capability. Current RET technology is applied in a one-shot fashion to the entire design at once. As a result, there's no way to make local, incremental changes. With Aprio's tools, users can verify optical-proximity-correction output, zoom in on problem areas, and make changes. Engineering change orders can be executed on the mask side. "This brings 'divide and conquer' into OPC," says Wu.

The first phase of Aprio's product rollout will occur in January with what the company terms "design-aware manufacturing tools." These will assist and/or replace existing RET enhancement and verification tools and handle ECOs incrementally. The second phase will bring "manufacturing-aware design tools." These tools could be announced at June's Design Automation Conference.

Aprio Technologies Inc.
www.aprio.com

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