With analog content on the rise in all manner of systems, it is more important than ever to integrate analog and mixed-signal capabilities into design and verification methodologies. What that means is an increasing reliance on Spice simulation for shakeout of the interface between the analog and digital domains of designs.
The problem for many, of course, is the time it takes to use Spice, even for critical paths that must be analyzed to the nth degree. A startup, Gemini Design Technology, thinks it may have the answer: parallelizing a 100% accurate flavor of Spice across multiple processing engines. In taking this approach, Gemini hopes to find the ultimate sweet spot between the speed offered by FastMOS simulators and the rigorous bug hunting of tuned Spice-accurate simulators.
Gemini Design Technology comes with an outstanding analog pedigree amongst its personnel. Perhaps the best thing Gemini Design Technology has going for it is the involvement, by way of financial backing and spiritual oversight, of Jim Solomon, the legendary analog wizard, co-founder of Cadence Design Systems and EDAC Phil Kaufman Award winner.
Solomon, a serial engineer-entrepreneur if ever there was one, sees in Gemini an opportunity to move Spice simulation in a modern direction on two fronts: the approach to simulation and the implementation of a multiprocessing paradigm.
In terms of approach, Gemini has spent three years building its simulator from the ground up to support a multi-threaded architecture. “We’ve had the advantage of starting with fundamentally better underlying mathematics and a better matrix solver,” says Kent Jaeger, Gemini’s vice president of marketing and sales.
According to Solomon, Gemini’s approach to multithreading of Spice is more holistic than previous attempts have been. “Cadence has only been able to multithread model evaluation,” says Solomon. “They don’t multithread any of the matrix solving.”
Gemini’s forthcoming simulator, which is expected to see initial production availability during the fourth quarter of 2008, approaches matrix solving by breaking up the overall circuit, sending it piecemeal to different processors, and then recombining the solved matrices into a seamless whole. “The magic is in recombining the matrices with no introduction of error,” says Solomon. “This has historically been impossible to achieve.” Solomon won’t delve further into how this is accomplished except to say that “the math is very subtle, and comparing our approach to what we know about others’ shows that theirs leads to non-robustness and a lack of convergence.”
According to Solomon, Gemini’s simulator will deliver the industry’s best performance scaling. “Because we have threaded the matrix solving and model solving, we scale with core complexity better than anyone else,” says Solomon. Gemini believes that the majority of applications can be handled by its simulator with machines having from four to 16 cores. Meanwhile, the simulator, as presently constituted, is fully capable of outputting 64 threads, which prepares it for significant extensibility.
In operation, the tool exhibits enough intelligence to automatically select how many threads it needs for a given netlist. It makes a determination based on the netlist’s complexity and the available compute resources.
As to performance claims based on early customer benchmarks, Gemini touts 2X to 10X speed improvement compared with single-threaded, Spice-accurate simulators. Some 90% of those benchmarks were performed under non-disclosure agreements, but according to Jaeger, the tool has been well evaluated. “We’ve been benchmarked with circuits from 300 transistors to 10 million elements on machines from one through 16 cores.”
Gemini Design Technology