Electronic Design

"Sugar" Sweetens System-Level Verficiation Flow

It's shaping up as the summer of assertion-based verification. Summit Design has debuted an assertion-based flow linking the Property Specification Language (formerly IBM's Sugar 2.0) with its Visual Elite functional modeling and verification tool.

Combining Visual Elite and IBM's "FoCs" tool, the new flow accelerates HDL and SystemC design and verification. Assertion-based verification lets designers define high-level functional rules (assertions or properties) that can be applied throughout the design process. It also helps find missed coverage at various abstraction levels.

Visual Elite is a C/C++ and SystemC functional modeling and verification environment that enables engineers to quickly capture and analyze complex hardware architectures and effectively map them to RTL implementation. FoCs takes Sugar assertions and transforms them to efficient assertion checking code, which can be integrated into the simulation environment. Combining FoCs and Visual Elite provides for dynamic assertion checking that greatly improves verification effectiveness.

Visual Elite is now in version 4.0. Major enhancements include Visual Elite Embedded System Co-design (ESC), a SystemC solution for target processors; and SystemC fast simulation and coding style utilizing FastC, a native SystemC text environment.

Visual Elite 4.0 is available now for beta trial with prices starting at $15,000.

Summit Design Inc.

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