Electronic Design

Suite Automates Hardware, Software, And System-Level Verification

In the electronic-system-level (ESL) realm, designers often can get a jumpstart on architectural definition and/or hardware/software co-design and verification. Yet the effort expended at these higher levels of abstraction is disconnected from the rest of the process.

Cadence s answer is to bring its plan-to-closure verification methodology to the ESL domain. Through a combination of hardware and software tools, Cadence plans to extend the traditional ESL approaches used at high abstraction levels to the rest of the enterprise. The plan-to-closure approach takes an enterprise-wide view of verification, accounting for the requirements of the various groups involved in the implementation process.

The ESL verification package encompasses three key components (see the figure). It delivers constrained-random and coverage-driven techniques to automate the generation of system scenarios. These scenarios expose functional bugs through combinations of software, hardware, and system-level interface transactions.

The methodology encompasses plan-and metric-driven verification management, extending those capabilities to embedded software and system-level efforts. All system-wide verification activities are tracked, analyzed, and compared against a predetermined verification plan to generate metrics.

Also part of the overall methodology is support for the Incisive Palladium III hardware emulator/accelerator. The system provides up to 2-MHz performance. Palladium III comes with a high-speed transaction interface to the Incisive Enterprise simulator. This environment also can be linked with a native, mixed-language, high-speed transaction interface to a SystemC model with speeds ranging from tens of kilohertz to the megahertz range.

For pricing and availability of the various elements of the ESL verification methodology, contact Cadence directly.

Cadence Design Systems

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