Electronic Design

Switch-Fabric Technology Enables On-Chip Networks

Traditional IC bus architectures are running out of steam. As engineers try to leverage more and more intellectual property (IP), hanging more IP blocks off of standard buses makes them wider and slower. This forces "mezzanining" into a proliferation of dedicated buses. Worse, those buses get clogged with interchip traffic.

Arteris SA, a French startup, may hold the answer to on-chip traffic management in its network-on-chip (NoC) technology. By combining IP offerings and a design tool suite as well as services, Arteris is betting that a switch-fabric architecture can be the bridge to future generations of extremely complex and high-performance ICs that will no longer suffer from the congestion in today's high-end systems-on-a-chip.

The technology hinges on basic IP building blocks consisting of switches, links, bridges, and memory controllers (see the figure). It's a packet-based technology that's homogeneous and fully scalable. Yet the on-chip network handles 100% of on-chip traffic requirements, including data, control, and I/O signaling. Arteris is circumspect about the protocol embodied in its packets, as the actual product won't roll out until later this year. But the packets are multipurpose in nature, and they serve to enable optimal wire efficiency.

The technology also employs a "globally asynchronous, locally synchronous" (GALS) approach where any number of switches and IP blocks can be defined as a synchronous subsystem. Multiple subsystems then can be connected asynchronously on a global basis for long-haul on-chip communication. Arteris says that the technique eases floorplanning and timing-closure issues.

The company's circumspection leaves some of the details of its technology lacking. In some ways, it's easier to say what Arteris' technology isn't—another IP socket technology in the mode of the Open Core Protocol. Yet the bridge IP included in Arteris' deliverables will make its network technology fully compatible with all existing IP socketing schemes, minimizing the rework required for individual IP blocks before integration.

A full suite of EDA tools will accompany the IP deliverables, with announcements of both coming later this year.

Arteris SA
www.arteris.net

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