Synopsys and UMC, the Taiwan-based semiconductor foundry, have added new capabilities to their jointly developed 90-nm reference design flow. The advanced low-power flow, initially introduced in November 2005, now includes an automated multiple voltage (multi-Vdd) capability that can significantly reduce dynamic power and leakage power dissipation. New design-for-test (DFT) capabilities have also been added to the flow, and existing design-for-manufacturing (DFM) capabilities were validated with UMC's libraries. These additions help IC companies reduce risk and achieve predictable success for complex low-power designs.
The RTL-to-GDSII reference flow helps designers address multi-voltage design challenges such as dynamic power and leakage, which are especially important in 90-nm designs. The reference flow features level shifter insertion, placement, optimization and verification, as well as voltage area (VA) creation and VA-aware physical optimization, clock-tree synthesis and routing. The timing closure flow includes signal-integrity (SI) prevention, repair and sign-off with multivoltage physical verification. In addition, the flow includes full-chip power analysis and power network analysis to ensure the power integrity of the design. Synopsys' DFT MAX scan compression automation solution is now included in the reference flow to enable higher test quality and to reduce tester application time. The 90-nm reference flow also features Synopsys' DFM technology for redundant via insertion, via-farm/via-array rules and timing-driven metal fill.
To validate the effectiveness of the reference flow, design consultants from Synopsys' Professional Services collaborated with UMC engineers to design a test chip with an open-source 32-bit RISC microprocessor core. The test chip, which was validated with UMC's library, was partitioned into multiple voltage regions and implemented using the advanced low-power reference flow. The core consisted of a SPARC-V8 compliant 32-bit RISC CPU, industry standard AMBA system buses, 10/100 Ethernet MAC and standard PCI interfaces. The chip is highly configurable and expandable for additional digital and/or analog/mixed-signal intellectual property (IP) modules.