Electronic Design
Synopsys Jumps Into ESL-Synthesis Pool

Synopsys Jumps Into ESL-Synthesis Pool


Interest in design at the electronic-system level (ESL) is surging as more design teams learn that algorithmic-intensive applications lend themselves nicely to such approaches. Not only is verification of both hardware and software quicker and easier, but there are now well-established methodologies for getting from highly abstract models to RTL.

This dovetails nicely with the reality that many IC designs in the wireless, wireline, multimedia, and set-top box markets are carrying a whole bunch of hard-coded algorithmic logic. In extreme cases, more than half the chips’ area is devoted to algorithmic content, especially in the standard-protocol-heavy segments such as multimedia and set-top boxes. Anyone who’s been involved in algorithm validation knows all too well that it’s never too early to ferret out all of the functional bugs. The ability to achieve early algorithmic validation is a major draw for ESL methodologies.

Now there’s another entry in the ESL synthesis marketplace in the form of the Synopsys Synphony high-level synthesis (HLS) tool, which the company has aimed directly at the heart of the burgeoning HLS market. Synphony is intended to synthesize algorithms written in the MathWorks’ Matlab (M) language into optimized RTL for ASICs, FPGAs, prototyping, and software development work. 

Today’s typical flow for development and validation of algorithmic functionality is fraught with risk. It’s labor-intensive and error-prone. Even worse, it can yield sub-optimal results. Synphony HLS lets you begin algorithmic design in the high-level Matlab environment, a milieu that is likely at least familiar to algorithmic designers (see the figure). In the MathWorks’ Simulink environment, users can design the algorithm and simulate its floating-point functionality before creating a fixed-point model. Alternatively, fixed-point blocks can be drawn from an IP library.

The tool’s M compiler offers features that derive fixed-point behavior directly from M code with guidance from the user’s fixed-point constraints. Once you have a fixed-point model that’s been tweaked into behaving as desired, the next step is to apply Synphony’s HLS engine to generate constrained and optimized RTL for implementation. Simultaneously, the tool generates an RTL testbench from the simulation used for the high-level models. It also generates a C model for further mixed-mode simulation.

Why use Matlab for creating floating-point algorithms? Basically, it’s a simpler way to work that requires far fewer lines of code for the same functionality as C code. It supports all of the most commonly used data types and functions. The fact that Synphony provides automatic compilation to fixed-point models is a bonus. This process provides rapid exploration of levels of fixed-point precision and eliminates a major source of bug introduction.

In the synthesis process, the tool optimizes the algorithm’s RTL for meeting timing and minimizing area and power. Four levels of optimization capability are available. At a system-wide level, the tool automatically determines where pipelining and scheduling are required and inserts them accordingly. It will also automatically select the correct IP architecture, perform automatic loop unrolling, and apply target-aware optimizations for FPGAs or ASICs.

For ASIC design, Synphony automatically generates RTL, constraints, and scripts for Design Compiler as well as a testbench and scripts for the VCS simulator. FPGA designers can enjoy an HLS flow that’s similar to that used by ASIC designers with FPGA-specific optimizations, such as optimized mapping to on-chip resources and advanced power estimation using the Synopsys Synplify Pro or Premier. The flow also lends itself to prototyping applications with the Synopsys HAPS and CHIPit lines of rapid prototyping hardware.

Synphony HLS is in beta release now with general availability scheduled by the end of 2009.

Synopsys Inc.

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