Designers generally regard synthesis as a process of moving from higher levels of abstraction to lower levels. But the emergence of higher-level design flows has triggered a need for high-level models.
Sometimes designers need to use an existing RTL IP block, but they want to use it in a high-level verification flow, which requires untimed, or minimally timed, SystemC models. Without such models, the legacy RTL code would slow the mixed-mode simulation.
Then there's the designer who, after some number of RTL simulations, decides to tweak a block of RTL code to achieve some performance goal or meet a constraint. Here, even if a high-level model of the original block existed, there's now a need for a new high-level model for use in the verification flow that reflects the change in functionality, however subtle. A couple of answers to this dilemma already exist in today's market.
First, Tenison EDA's tools enable designers to bring an RTL block back up to whatever level of abstraction they choose, whether it's an untimed high-speed model or cycle-accurate model. Tenison achieves a kind of "reverse synthesis" in a sense, transforming a lower-level design representation into a higher-level one. In the process, the higher-level models enable designers to capitalize on their ESL verification tools.
Another answer comes from Carbon Design Systems, whose Virtual Silicon Prototypes platform permits the combined validation of multiple abstraction levels. Under the hood is Carbon's RTL compilation technology; system building blocks including transactors, memories, and IP cores; and tight integration with SystemC and popular instruction-set simulators.
Either of these approaches can help designers who need to "back up" from RTL to higher levels of abstraction, particularly for verification purposes.