By predicting circuit congestion “hot spots” early in the design flow, Synopsys’ Design Compiler Graphical synthesis tool helps RTL designers avoid problems during the detailed routing of their systems-on-a-chip (SoCs). The tool provides visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in those areas.
Even if a design meets all the performance specifications, congestion can be severe enough to make it very difficult to successfully route the design, leading to longer design cycles and more iterations between synthesis and place-and-route. The ability to predict, visualize and alleviate routing problems prior to physical implementation substantially reduces iterations between synthesis and place-and-route, and can significantly lower project time, effort and cost.
Design Compiler Graphical circumvents these iterations, which can be especially lengthy and painstaking for very large designs. First, it provides congestion reports and visualization to assist designers in identifying congested regions in a circuit. Second, it employs optimization techniques to synthesize a design with significantly less congestion, thereby creating a better starting point for physical design. The ability to first estimate and then prevent routing congestion problems early in the design phase produces a more predictable, streamlined design flow from RTL synthesis through physical implementation that can shave weeks off project schedules.
Design Compiler Graphical is available today as an add-on to DC Ultra. Contact Synopsys directly for pricing details.