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System-On-Chip Verification Is Taken To Transistor Level

The Affirma accelerated transistor-level simulator is a key to enabling verification of systems-on-a-chip and other large, digital-centric, mixed-signal designs. The tool is said to provide a proven architecture for timing and power analysis of transistor-level mixed-signal designs. The simulator combines the high speed of a digital MOS timing algorithm for Fast-MOS simulation with the accuracy of a traditional, Spice-like analog algorithm to concurrently simulate the analog and digital portions of a mixed-signal IC at the transistor level. The combination allows the use of a single engine to simulate large, complex designs, such as SOCs, large ASICs with embedded analog circuitry, structured custom designs, and more.


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