EE Product News

System-On-Chip Verification Is Taken To Transistor Level

The Affirma accelerated transistor-level simulator is a key to enabling verification of systems-on-a-chip and other large, digital-centric, mixed-signal designs. The tool is said to provide a proven architecture for timing and power analysis of transistor-level mixed-signal designs. The simulator combines the high speed of a digital MOS timing algorithm for Fast-MOS simulation with the accuracy of a traditional, Spice-like analog algorithm to concurrently simulate the analog and digital portions of a mixed-signal IC at the transistor level. The combination allows the use of a single engine to simulate large, complex designs, such as SOCs, large ASICs with embedded analog circuitry, structured custom designs, and more.

Company: CADENCE DESIGN SYSTEMS INC.

Product URL: Click here for more information

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish