Based on an innovative PLD architecture, APEX 20K programmable logic devices (PLDs) are said to represent the industry's first programmable chips to contain an entire complex system. The architecture is claimed to be the first to successfully integrate product-term and look-up-table functionality along with embedded memory. APEX family gate count is expected to range from 100,000 to 1,000,000.Fabricated using a 0.25-µm (drawn), six-layer SRAM process, model EP20K400, the first member of the APEX 20K family, features 16,640 logic elements, 104 embedded system blocks, 1664 macrocells, and 212,992 bits of on-chip RAM for a total of approximately 400,000 gates. The RAM can be configured as dual-port RAM, ROM, or as product-term logic. The EP20K400 system-on-a-programmable-chip offers 125-MHz system performance and enhanced PLL with 1x, 2x and 4x clock rate multiplying options. It's shipping now in a 655-pin PGA package, with 652-pin BGAs and 672-pin Fineline BGAs to follow. The APEX family is fully supported by the firm's powerful Quartus development environment.