SystemC Draws Interest From Target Group

Sept. 15, 2003
In the several years since it first arrived, the SystemC modeling platform and design language has struggled with an identity crisis. Is it for designers of bleeding-edge processors from the likes of Intel or nVidia, or for the systems houses in which...

In the several years since it first arrived, the SystemC modeling platform and design language has struggled with an identity crisis. Is it for designers of bleeding-edge processors from the likes of Intel or nVidia, or for the systems houses in which application-specific standard products and systems-on-a-chip (SoCs) are carefully crafted for specialized uses?

From three separate surveys of users, it's clear that SystemC is finding its niche. Interest in the language is growing and, more importantly, it's growing among the users for whom it was originally intended−SoC architects at systems houses.

According to Open SystemC Initiative (OSCI) president Kevin Kranen, data from user surveys in Europe, Japan, and the U.S. show a shift in how designers regard SystemC. "When we first launched SystemC, it might not have been clear that it wasn't meant to replace Verilog or the implementation flow that's in place in most semiconductor companies," he says. The hostility that's been expressed toward SystemC by hardcore IC implementation specialists may have been overdone.

While user surveys still don't rank SystemC very highly as a hardware design language, interest in it is burgeoning for software design, abstract algorithm modeling, software coverification, design partitioning, and creation of "golden" models of system functionality. In other words, says Kranen, designers are seeing SystemC for what it was originally intended, namely high-level architectural exploration.

This is echoed by the results of a survey taken at the 3rd Japan SystemC User's Forum early this year. Over 400 attendees completed 320 questionnaires, and it was found that a large majority uses SystemC for system-level modeling and/or testbench creation and verification (see the figure).

Europe's SystemC users, in particular, are making strides toward inserting SystemC into the system design process. European designers have long favored VHDL over Verilog for its system-level constructs, and Kranen now sees a shift from VHDL to SystemC under way in some of Europe's system-level houses.

Meanwhile, there's been a change in the population attending the technology symposium OSCI holds each year at the Design Automation Conference (DAC).

"It's moved from a mix of semiconductor and systems guys to mostly systems guys," says Kranen. Whereas 21% of 2002 attendees identified themselves as system-level designers, that number rose to 30% in 2003. Meanwhile, semiconductor designers dropped from 24% in 2002 to 14% in 2003.

Fully half of the DAC attendees polled said that an automatic path to implementation was what SystemC needs most. This is, as Kranen puts it, the "holy grail" that will take time to arrive, if ever. Meanwhile, the user community for SystemC continues to expand.

Open SystemC Initiativewww.systemc.org

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